understand now，thanks for the explaination, I will update it. 发件人：Peter Maydell <peter.mayd...@linaro.org> 收件人：gengdongjiu <gengdong...@huawei.com> 抄 送：qemu-arm <qemu-...@nongnu.org>;QEMU Developers <qemu-devel@nongnu.org> 时间：2019-03-11 23:39:32 主 题：Re: [RESEND PATCH] target/arm: change arch timer registers access permission
On Mon, 11 Mar 2019 at 15:24, gengdongjiu <gengdong...@huawei.com> wrote: > So If QEMU defined the timer registers read only in PL0, even though it has > been configured to have write permission in PL0 by high PLx, we still cannot > have > Write permission, because QEMU will firstly check the defined permission and > then check the configured permission by high PLx. I'm afraid I don't understand what you're trying to say here. Yes, it was a bug that we marked these registers as read-only for PL0, and we should fix it. What I am trying to say is that .access = PL1_RW | PL0_RW is exactly equivalent to .access = PL0_RW and we should use the simpler version of the expression. (If you look at the definitions of all the PL*_ constants, you can see that PL0_W implies PL1_W: #define PL0_W (0x01 | PL1_W) and similarly for PL0_R. So all the bits in the bitfield that would be set by PL1_RW are also set by PL0_RW.) thanks -- PMM
