Re: [Qemu-devel] [PATCH v5 00/35] target/riscv: Convert to decodetree

[Bastian Koppelmann]

On 1/22/19 10:38 PM, Richard Henderson wrote:
On 1/22/19 1:28 AM, Bastian Koppelmann wrote:
Hi,

this patchset converts the RISC-V decoder to decodetree in four major steps:

1) Convert 32-bit instructions to decodetree [Patch 1-16]:
     Many of the gen_* functions are called by the decode functions for 16-bit
     and 32-bit functions. If we move translation code from the gen_*
     functions to the generated trans_* functions of decode-tree, we get a lot 
of
     duplication. Therefore, we mostly generate calls to the old gen_* function
     which are properly replaced after step 2).

     Each of the trans_ functions are grouped into files corresponding to their
     ISA extension, e.g. addi which is in RV32I is translated in the file
     'trans_rvi.inc.c'.

2) Convert 16-bit instructions to decodetree [Patch 17-19]:
     All 16 bit instructions have a direct mapping to a 32 bit instruction. 
Thus,
     we convert the arguments in the 16 bit trans_ function to the arguments of
     the corresponding 32 bit instruction and call the 32 bit trans_ function.

3) Remove old manual decoding in gen_* function [Patch 20-30]:
     this move all manual translation code into the trans_* instructions of
     decode tree, such that we can remove the old decode_* functions.

4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
    by Richard. [Patch 31-35]

full tree available at
https://github.com/bkoppelmann/qemu/tree/riscv-dt-v5

Cheers,
Bastian

v4 -> v5:
     - fixed rebase error
     - moved TARGET_LONG_BITS check of shift instructions before rd == 0 check
     - removed extra sign extension of sraiw
     - removed rs2 == 0 special cases in sraw/srlw
All looks good to me now.  Thanks for persevering.


Thanks for your great reviews. I'll do a final respin to fix the funky 
indentations. Alistair do you want to pick up the series?

Cheers,

Bastian