On 1/17/19 7:23 AM, Alex Bennée wrote: > Apparently some versions of clang can't handle inline assembly with > __int128 parameters, especially on s390. Instead of hand-coding the > s390 divide provide a generic fallback for anything that provides > __int128 capable maths. > > Signed-off-by: Alex Bennée <[email protected]> > Cc: Thomas Huth <[email protected]> > --- > include/fpu/softfloat-macros.h | 10 ++++------ > 1 file changed, 4 insertions(+), 6 deletions(-) > > diff --git a/include/fpu/softfloat-macros.h b/include/fpu/softfloat-macros.h > index b1d772e6d4..1a43609eef 100644 > --- a/include/fpu/softfloat-macros.h > +++ b/include/fpu/softfloat-macros.h > @@ -641,12 +641,6 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t > n1, > uint64_t q; > asm("divq %4" : "=a"(q), "=d"(*r) : "0"(n0), "1"(n1), "rm"(d)); > return q; > -#elif defined(__s390x__) > - /* Need to use a TImode type to get an even register pair for DLGR. */ > - unsigned __int128 n = (unsigned __int128)n1 << 64 | n0; > - asm("dlgr %0, %1" : "+r"(n) : "r"(d)); > - *r = n >> 64; > - return n; > #elif defined(_ARCH_PPC64) && defined(_ARCH_PWR7) > /* From Power ISA 2.06, programming note for divdeu. */ > uint64_t q1, q2, Q, r1, r2, R; > @@ -663,6 +657,10 @@ static inline uint64_t udiv_qrnnd(uint64_t *r, uint64_t > n1, > } > *r = R; > return Q; > +#elif defined(CONFIG_INT128) > + unsigned __int128 n = (unsigned __int128)n1 << 64 | n0; > + *r = n % d; > + return n / d; > #else
I thought that we'd shown that, at least at present, no compiler is taking advantage of hardware insns for this, and is promoting this to a full 128-bit divide. And further that the version using 64-bit arithmetic was competitive with the hardware insn. I'd rather not include this hunk for now. r~
