On 2 November 2018 at 13:41, Richard Henderson
<[email protected]> wrote:
> The bulk of the work here, beyond base HPD, is defining the TTBCR2 register.
> In addition we must check TTBCR.T2E, which is not present (RES0) for AArch64.
>
> Signed-off-by: Richard Henderson <[email protected]>
> ---
> target/arm/cpu.h | 8 ++++++++
> target/arm/cpu.c | 4 ++++
> target/arm/helper.c | 37 +++++++++++++++++++++++++++++--------
> 3 files changed, 41 insertions(+), 8 deletions(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index f12a6afddc..a253cdebde 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -1517,6 +1517,14 @@ FIELD(ID_ISAR6, FHM, 8, 4)
> FIELD(ID_ISAR6, SB, 12, 4)
> FIELD(ID_ISAR6, SPECRES, 16, 4)
>
> +FIELD(ID_MMFR4, SPECSEI, 0, 4)
> +FIELD(ID_MMFR4, AC2, 4, 4)
> +FIELD(ID_MMFR4, XNX, 8, 4)
> +FIELD(ID_MMFR4, CNP, 12, 4)
> +FIELD(ID_MMFR4, HPDS, 16, 4)
> +FIELD(ID_MMFR4, LSM, 20, 4)
> +FIELD(ID_MMFR4, CCIDX, 24, 4)
Maybe add the v8.5 field too?
FIELD(ID_MMFR4, EVT, 28, 4)
> +/* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
> + * qemu tlbs nor adjusting cached masks.
> + */
> +static const ARMCPRegInfo ttbcr2_reginfo = {
> + .name = "TTBCR2", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 3,
Our usual order for these fields is cp, opc1, crn, crm, opc2.
> + .access = PL1_RW, .type = ARM_CP_ALIAS,
> + .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]),
> + offsetofhigh32(CPUARMState, cp15.tcr_el[1]) },
> +};
Otherwise
Reviewed-by: Peter Maydell <[email protected]>
thanks
-- PMM
