On 1 November 2018 at 17:26, Alex Bennée <[email protected]> wrote: > > Richard Henderson <[email protected]> writes: > >> My previous patch set for replacing feature bits with id registers >> failed to consider that these id registers are beginning to control >> migration, and thus we must fill them in for KVM as well. >> >> Thus, we want to initialize these values within CPU from the host. >> >> Finally, re-send the T32EE conversion patch, fixing the build >> failure on an arm32 host in kvm32.c. >> >> Tested on arm64; cross-build tested for arm32. > > I'm still seeing the following assert on qemu-test: > > qemu-system-aarch64: /home/alex/lsrc/qemu.git/target/arm/cpu.c:832: > arm_cpu_realizefn: Assertion `cpu_isar_feature(arm_div, cpu)' failed. > > Which is a regression caused by: > > 7e0cf8b: target/arm: Convert division from feature bits to isar0 tests > > I think the problem is the we trip over the assert because: > > /* Some features automatically imply others: */ > if (arm_feature(env, ARM_FEATURE_V8)) { > if (arm_feature(env, ARM_FEATURE_M)) { > set_feature(env, ARM_FEATURE_V7); > } else { > set_feature(env, ARM_FEATURE_V7VE); > } > } > > Allows: > > if (arm_feature(env, ARM_FEATURE_V7VE)) { > assert(cpu_isar_feature(arm_div, cpu)); > > Which isn't strictly true on kvm guests.
KVM guests should definitely all be v7VE and all have the arm divide instruction, if they implement AArch32 at all. I think what we're hitting here is the case where the host CPU has no AArch32 support. In that case the ID_ISAR0_EL1 sysreg (which we read from KVM and use to populate the cpu->isar struct) has an UNKNOWN value. thanks -- PMM
