On 30/10/18 16:44, Aleksandar Markovic wrote:
From: Aleksandar Markovic <[email protected]>
Misc changes in comments and strings for R5900.
Reviewed-by: Stefan Markovic <[email protected]>
Signed-off-by: Aleksandar Markovic <[email protected]>
---
target/mips/translate_init.inc.c | 12 ------------
1 file changed, 12 deletions(-)
diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.inc.c
index 85da4a2..cab2003 100644
--- a/target/mips/translate_init.inc.c
+++ b/target/mips/translate_init.inc.c
@@ -411,18 +411,6 @@ const mips_def_t mips_defs[] =
.mmu_type = MMU_TYPE_R4000,
},
{
- /*
- * The Toshiba TX System RISC TX79 Core Architecture manual
- *
- * https://wiki.qemu.org/File:C790.pdf
I still think a single line comment with this URL is well placed here.
This is the entry point to all R5900 specific code.
Anyway, your call.
- *
- * describes the C790 processor that is a follow-up to the R5900.
- * There are a few notable differences in that the R5900 FPU
- *
- * - is not IEEE 754-1985 compliant,
- * - does not implement double format, and
- * - its machine code is nonstandard.
- */
.name = "R5900",
.CP0_PRid = 0x00002E00,
/* No L2 cache, icache size 32k, dcache size 32k, uncached coherency.
*/
