On 9/30/18 6:14 PM, Maciej W. Rozycki wrote:
> On Sun, 30 Sep 2018, Philippe Mathieu-Daudé wrote:
>
>>> + MIPS_INVAL("mul R5900");
>>
>> I'd use:
>>
>> MIPS_INVAL("mul/div Toshiba");
>
> But just like `gen_mul_vr54xx' this function doesn't handle division!
Per the commit message, I understood this function would eventually
handle "the R5900 specific pipeline 1 instruction variants MULT1,
MULTU1, DIV1, DIVU1, ..."
>
>>> @@ -22378,6 +22449,8 @@ static void decode_opc_special_legacy(CPUMIPSState
>>> *env, DisasContext *ctx)
>>> check_insn(ctx, INSN_VR54XX);
>>> op1 = MASK_MUL_VR54XX(ctx->opcode);
>>> gen_mul_vr54xx(ctx, op1, rd, rs, rt);
>>> + } else if (ctx->insn_flags & INSN_R5900) {
>>> + gen_mul_txxx(ctx, op1, 0, rd, rs, rt);
>>
>> Similarly, I'd name this gen_muldiv_txx9().
>
> Likewise. I agree with the `_txx9' suffix update, it makes sense to me.
Cool, thanks.
