From: Michael Clark <[email protected]> Cc: Sagar Karandikar <[email protected]> Cc: Bastian Koppelmann <[email protected]> Cc: Palmer Dabbelt <[email protected]> Cc: Alistair Francis <[email protected]> Signed-off-by: Palmer Dabbelt <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Signed-off-by: Alistair Francis <[email protected]> --- target/riscv/cpu.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 34abc383e3..e0608e6d5f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -24,12 +24,12 @@ #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ #if defined(TARGET_RISCV64) #define TARGET_LONG_BITS 64 -#define TARGET_PHYS_ADDR_SPACE_BITS 50 -#define TARGET_VIRT_ADDR_SPACE_BITS 39 +#define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */ +#define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */ #elif defined(TARGET_RISCV32) #define TARGET_LONG_BITS 32 -#define TARGET_PHYS_ADDR_SPACE_BITS 34 -#define TARGET_VIRT_ADDR_SPACE_BITS 32 +#define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */ +#define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ #endif #define TCG_GUEST_DEFAULT_MO 0 -- 2.17.1
