On 08/24/2018 12:44 PM, Craig Janeczek via Qemu-devel wrote:
> + case OPC_MXU_S8LDD:
> + gen_load_gpr(t0, opcode->S8LDD.rb);
> + tcg_gen_movi_tl(t1, opcode->S8LDD.s8);
> + tcg_gen_ext8s_tl(t1, t1);
> + tcg_gen_add_tl(t0, t0, t1);
This is
gen_load_gpr(t0, rb);
tcg_gen_addi_tl(t0, t0, (int8_t)s8);
> + tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_SB);
You might want MO_UB so that you don't need
tcg_gen_andi_tl(t1, t1, 0xff)
in several places.
Hmm. Of course there's the two sign-extend cases that do want this. So maybe
some more logic above the load is warranted.
> + switch (opcode->S8LDD.optn3) {
> + case 0: /*XRa[7:0] = tmp8 */
> + tcg_gen_andi_tl(t1, t1, 0xFF);
> + gen_load_mxu_gpr(t0, opcode->S8LDD.xra);
> + tcg_gen_andi_tl(t0, t0, 0xFFFFFF00);
> + tcg_gen_or_tl(t0, t0, t1);
gen_load_mxu_gpr(t0, xra);
tcg_gen_deposit_tl(t0, t0, t1, 0, 8);
> + break;
> + case 1: /* XRa[15:8] = tmp8 */
> + tcg_gen_andi_tl(t1, t1, 0xFF);
> + gen_load_mxu_gpr(t0, opcode->S8LDD.xra);
> + tcg_gen_andi_tl(t0, t0, 0xFFFF00FF);
> + tcg_gen_shli_tl(t1, t1, 8);
> + tcg_gen_or_tl(t0, t0, t1);
tcg_gen_deposit_tl(t0, t0, t1, 8, 8);
> + case 4: /* XRa = {8'b0, tmp8, 8'b0, tmp8} */
> + tcg_gen_andi_tl(t1, t1, 0xFF);
> + tcg_gen_mov_tl(t0, t1);
> + tcg_gen_shli_tl(t1, t1, 16);
> + tcg_gen_or_tl(t0, t0, t1);
> + break;
tcg_gen_deposit_tl(t0, t1, t1, 16, 16);
> + case 5: /* XRa = {tmp8, 8'b0, tmp8, 8'b0} */
> + tcg_gen_andi_tl(t1, t1, 0xFF);
> + tcg_gen_shli_tl(t1, t1, 8);
> + tcg_gen_mov_tl(t0, t1);
> + tcg_gen_shli_tl(t1, t1, 16);
> + tcg_gen_or_tl(t0, t0, t1);
tcg_gen_shli_tl(t1, t1, 8);
tcg_gen_deposit_tl(t0, t1, t1, 16, 16);
> + case 7: /* XRa = {tmp8, tmp8, tmp8, tmp8} */
> + tcg_gen_andi_tl(t1, t1, 0xFF);
> + tcg_gen_mov_tl(t0, t1);
> + tcg_gen_shli_tl(t1, t1, 8);
> + tcg_gen_or_tl(t0, t0, t1);
> + tcg_gen_shli_tl(t1, t1, 8);
> + tcg_gen_or_tl(t0, t0, t1);
> + tcg_gen_shli_tl(t1, t1, 8);
> + tcg_gen_or_tl(t0, t0, t1);
tcg_gen_muli_tl(t0, t1, 0x01010101);
r~
