On Tue, Aug 14, 2018 at 01:42:51PM +0100, Peter Maydell wrote: > The AArch32 HSR is the equivalent of AArch64 ESR_EL2; > we can implement it by marking our existing ESR_EL2 regdef > as STATE_BOTH. It also needs to be "RES0 from EL3 if > EL2 not implemented", so add the missing stanza to > el3_no_el2_cp_reginfo.
Reviewed-by: Edgar E. Iglesias <[email protected]> > > Signed-off-by: Peter Maydell <[email protected]> > --- > target/arm/helper.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index d6e98e9d606..80855302089 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -3763,6 +3763,10 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = { > .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 4, > .access = PL2_RW, > .type = ARM_CP_CONST, .resetvalue = 0 }, > + { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, > + .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, > + .access = PL2_RW, > + .type = ARM_CP_CONST, .resetvalue = 0 }, > { .name = "CPTR_EL2", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 2, > .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, > @@ -3926,7 +3930,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { > .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1, > .access = PL2_RW, > .fieldoffset = offsetof(CPUARMState, elr_el[2]) }, > - { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64, > + { .name = "ESR_EL2", .state = ARM_CP_STATE_BOTH, > .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0, > .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) > }, > { .name = "FAR_EL2", .state = ARM_CP_STATE_BOTH, > -- > 2.18.0 >
