This patchset fixes two issues: * default_nan_mode not being honoured for float-to-float conversions * half precision conversions being broken in a number of ways as well as not handling default_nan_mode.
With this patchset qemu passes random-instruction-selection tests for VCVT.F32.F16, VCVT.F16.F32, VCVTB and VCVTT, in both IEEE and non-IEEE modes, with and without default-NaN behaviour. Christophe: this patchset includes your softfloat v3 patch, although I have split it up a little to keep the float16 bits separate. Changes since v2: * added STRUCT_TYPES version of float16 and fixed various places which needed a make_float16()/float16_val() in order to compile with STRUCT_TYPES enabled * s/bits16/float16/ in patch 3 as suggested by Aurelien * fixed the types in the f16-related ARM helper wrappers in patch 6 Patch 2 is unchanged and so I've added Aurelien's reviewed-by signoff; the others all changed, although mostly in minor ways. (Compiling with STRUCT_TYPES enabled also needs some fixes to existing float32/float64 code; I'll send a separate patchset for that.) Christophe Lyon (1): softfloat: Honour default_nan_mode for float-to-float conversions Peter Maydell (5): softfloat: Add float16 type and float16 NaN handling functions softfloat: Fix single-to-half precision float conversions softfloat: Correctly handle NaNs in float16_to_float32() target-arm: Silence NaNs resulting from half-precision conversions target-arm: Use standard FPSCR for Neon half-precision operations fpu/softfloat-specialize.h | 130 ++++++++++++++++++++++++++++++++++++++++++-- fpu/softfloat.c | 100 ++++++++++++++++++++++------------ fpu/softfloat.h | 19 ++++++- target-arm/helper.c | 38 +++++++++++-- target-arm/helpers.h | 2 + target-arm/translate.c | 16 +++--- 6 files changed, 251 insertions(+), 54 deletions(-)
