On Sat, Jun 30, 2018 at 10:32 AM, Richard Henderson <[email protected]> wrote: > On 06/22/2018 06:58 AM, Peter Maydell wrote: >> The xtensa frontend calls get_page_addr_code() from its >> itlb_hit_test helper function. This function is really part >> of the TCG core's internals, and calling it from a target >> helper makes it awkward to make changes to that core code. >> It also means that we don't pass the correct retaddr to >> tlb_fill(), so we won't correctly handle the case where >> an exception is generated. >> >> The helper is used for the instructions IHI, IHU and IPFL. > > I think the implementation of these instructions is completely wrong. > > (1a) IHI is not invalidating the cacheline within env->config->itlb, > (1b) IHI is not invalidating the qemu TLB that might contain a copy > of same. > (2a) IPFL is not locking the entry in env->config->itlb, > (2b) IHU is not unlocking the same entry.
All the above instructions are meant to invalidate cache, not the TLB. > (2c) "Xtensa ISA implementations that do not implement cache locking > must raise an illegal instruction exception when [IPFL or IHU] > is executed." They will raise an illegal instruction exception, because such CPUs will not recognize these instructions in the xtensa_opcode_decode. I believe that the implementation we have currently is rather accurate. -- Thanks. -- Max
