On 12 June 2018 at 07:57, Cédric Le Goater <c...@kaod.org> wrote: > Hello, > > Here is a short series of cleanups and fixes for issues in the Aspeed > SMC controller model discovered when experimenting with the MMIO exec > feature and also from tests under a QEMU PowerNV machine. > > Indeed, the OPAL/skiboot firmware accesses the Aspeed SoC address > space using the iLPC->AHB bridge of the SuperIO controller and drives > the SPI controller to access the PNOR. > > Thanks, > > C. > > Cédric Le Goater (3): > aspeed/smc: fix dummy cycles count when in dual IO mode > aspeed/smc: fix HW strapping > aspeed/smc: rename aspeed_smc_flash_send_addr() to aspeed_smc_flash_setup()
Applied to target-arm.next, thanks. -- PMM
