Thanks for the feedback Peter. Removing the redundant check on bit 23 and adding checks for the "should be" bits as well (bits [11:8]).
The following patch should make sure we are not treating architecturally Undefined instructions as a SWP, by verifying the opcodes as per section A8.8.229 of ARMv7-A specification. Best, Onur Signed-off-by: Onur Sahin <[email protected]> --- target/arm/translate.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index ba6ab7d..1fb0b8f 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9227,11 +9227,14 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) } } tcg_temp_free_i32(addr); - } else { + } else if ((insn & 0x00300f00) == 0) { + /* 0bcccc_0001_0x00_xxxx_xxxx_0000_1001_xxxx + * - SWP, SWPB + */ + TCGv taddr; TCGMemOp opc = s->be_data; - /* SWP instruction */ rm = (insn) & 0xf; if (insn & (1 << 22)) { @@ -9249,6 +9252,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) get_mem_index(s), opc); tcg_temp_free(taddr); store_reg(s, rd, tmp); + } else { + goto illegal_op; } } } else { -- 1.8.3.1
