Hi Aaron,
On 03/16/2018 09:31 PM, Aaron Lindsay wrote:
> This is a bug fix to ensure 64-bit reads of this register don't read
> adjacent data.
>
> Signed-off-by: Aaron Lindsay <[email protected]>
> ---
> target/arm/cpu.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index 9c3b5ef..fb2f983 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -367,7 +367,7 @@ typedef struct CPUARMState {
> uint32_t c9_data;
> uint64_t c9_pmcr; /* performance monitor control register */
> uint64_t c9_pmcnten; /* perf monitor counter enables */
> - uint32_t c9_pmovsr; /* perf monitor overflow status */
> + uint64_t c9_pmovsr; /* perf monitor overflow status */
This doesn't look correct, since this reg is 32b.
I *think* the correct fix is in ARMCPRegInfo v7_cp_reginfo[]:
{ .name = "PMOVSR", ...
- ..., .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
+ ..., .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
.accessfn = pmreg_access,
.writefn = pmovsr_write,
.raw_writefn = raw_write },
> uint32_t c9_pmuserenr; /* perf monitor user enable */
> uint64_t c9_pmselr; /* perf monitor counter selection register */
> uint64_t c9_pminten; /* perf monitor interrupt enables */
>
Regards,
Phil.
