On 28 February 2018 at 19:31, Richard Henderson <[email protected]> wrote: > Signed-off-by: Richard Henderson <[email protected]> > --- > target/arm/translate.c | 68 > ++++++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 68 insertions(+) > > diff --git a/target/arm/translate.c b/target/arm/translate.c > index 9169b6b367..45513c9d86 100644 > --- a/target/arm/translate.c > +++ b/target/arm/translate.c > @@ -7680,6 +7680,68 @@ static int disas_neon_data_insn(DisasContext *s, > uint32_t insn) > return 0; > } > > +/* Advanced SIMD three registers of the same length extension. > + * 31 25 23 22 20 16 12 11 10 9 8 3 > 0 > + * > +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+ > + * | 1 1 1 1 1 1 0 | op1 | D | op2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U | > Vm | > + * > +---------------+-----+---+-----+----+----+---+----+---+----+---------+----+ > + */ > +static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) > +{ > + gen_helper_gvec_3_ptr *fn_gvec_ptr; > + int rd, rn, rm, rot, size, opr_sz; > + TCGv_ptr fpst; > + bool q; > + > + q = extract32(insn, 6, 1); > + VFP_DREG_D(rd, insn); > + VFP_DREG_N(rn, insn); > + VFP_DREG_M(rm, insn); > + if ((rd | rn | rm) & q) { > + return 1; > + } > + > + if ((insn & 0xfe200f10) == 0xfc200800) {
Slightly confusing to be re-checking bits we've already decoded, rather than just looking at op1/op2/op3/op4/Q/U. Anyway Reviewed-by: Peter Maydell <[email protected]> thanks -- PMM
