Hi,
port->ctrl = (port->ctrl& 0x01fb) | (val& ~0x01fb);
/* some bits are reset when a '1' is written to them */
port->ctrl&= ~(val& 0x000a);
+ port->ctrl&= ~(port->ctrl& 0x0040); /* clear port resume detected
*/
Removing the port resume bit from the readonly mask works better than the clear-on-any-write hack ;)
cheers, Gerd
