On Fri, Jul 14, 2017 at 23:42:33 -1000, Richard Henderson wrote:
> From: Lluís Vilanova <[email protected]>
>
> Incrementally paves the way towards using the generic instruction translation
> loop.
>
> Signed-off-by: Lluís Vilanova <[email protected]>
> Message-Id: <[email protected]>
> [rth: Adjust for translate_insn interface change.]
> Signed-off-by: Richard Henderson <[email protected]>
(snip)
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -11842,6 +11842,8 @@ static int arm_tr_init_disas_context(DisasContextBase
> *dcbase,
> dc->is_ldex = false;
> dc->ss_same_el = false; /* Can't be true since EL_d must be AArch64 */
>
> + dc->next_page_start =
> + (dc->base.pc_first & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
>
> cpu_F0s = tcg_temp_new_i32();
> cpu_F1s = tcg_temp_new_i32();
> @@ -11935,14 +11937,93 @@ static bool
> arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
> return true;
> }
>
> +static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
> +{
> + DisasContext *dc = container_of(dcbase, DisasContext, base);
> + CPUARMState *env = cpu->env_ptr;
> +
> +#ifdef CONFIG_USER_ONLY
> + /* Intercept jump to the magic kernel page. */
> + if (dc->pc >= 0xffff0000) {
> + /* We always get here via a jump, so know we are not in a
> + conditional execution block. */
> + gen_exception_internal(EXCP_KERNEL_TRAP);
> + dc->base.is_jmp = DISAS_NORETURN;
> + return;
> + }
> +#endif
Nit: Indent this properly here to avoid the indent fix in patch 33.
E.
