On 2017-07-06 16:21, Richard Henderson wrote:
> This enforces proper alignment and makes the register update
> more natural. Note that there is a more serious bug fix for
> fmov {DX}Rn,@(R0,Rn) to use a store instead of a load.
>
> Signed-off-by: Richard Henderson <[email protected]>
> ---
> target/sh4/translate.c | 74
> ++++++++++++++++++++++++--------------------------
> 1 file changed, 35 insertions(+), 39 deletions(-)
>
> diff --git a/target/sh4/translate.c b/target/sh4/translate.c
> index 616e615..fcdabe8 100644
> --- a/target/sh4/translate.c
> +++ b/target/sh4/translate.c
> @@ -1044,18 +1038,20 @@ static void _decode_opc(DisasContext * ctx)
> return;
> case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
> CHECK_FPU_ENABLED
> - TCGv addr = tcg_temp_new_i32();
> - tcg_gen_subi_i32(addr, REG(B11_8), 4);
> - if (ctx->tbflags & FPSCR_SZ) {
> - int fr = XHACK(B7_4);
> - tcg_gen_qemu_st_i32(FREG(fr + 1), addr, ctx->memidx, MO_TEUL);
> - tcg_gen_subi_i32(addr, addr, 4);
> - tcg_gen_qemu_st_i32(FREG(fr), addr, ctx->memidx, MO_TEUL);
> - } else {
> - tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL);
> - }
> - tcg_gen_mov_i32(REG(B11_8), addr);
> - tcg_temp_free(addr);
> + {
> + TCGv addr = tcg_temp_new_i32();
> + if (ctx->tbflags & FPSCR_SZ) {
> + TCGv_i64 fp = tcg_temp_new_i64();
> + gen_load_fpr64(ctx, fp, XHACK(B7_4));
> + tcg_gen_qemu_st_i64(fp, addr, ctx->memidx, MO_TEQ);
addr is used without before being written. The following line is mising
before the load:
tcg_gen_subi_i32(addr, REG(B11_8), 8);
> + tcg_temp_free_i64(fp);
> + } else {
> + tcg_gen_subi_i32(addr, REG(B11_8), 4);
> + tcg_gen_qemu_st_i32(FREG(B7_4), addr, ctx->memidx, MO_TEUL);
> + }
> + tcg_gen_mov_i32(REG(B11_8), addr);
> + tcg_temp_free(addr);
> + }
> return;
> case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
> CHECK_FPU_ENABLED
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
[email protected] http://www.aurel32.net
