Hi Pasha,
On Tue, Jun 27, 2017 at 7:59 PM, Pasha Tatashin
<pasha.tatas...@oracle.com> wrote:
> Hi,
>
> I am trying to evaluate the current qemu support for sparc64 processors.
> First, it seems -smp is not supported for any processor, is this correct?
> When I set -smp greater than 1, I am getting:
>
> qemu-system-sparc64: Number of SMP CPUs requested (2) exceeds max CPUs
> supported by machine 'sun4u' (1)
>
> I've done some testing for all available sparc64 cpus + latest linux kernel:
>
> Fujitsu Sparc64 Working
> Fujitsu Sparc64 III Exception 0x30 (DAE_side_effect_page) in OpenBios
> Fujitsu Sparc64 IV Working
> Fujitsu Sparc64 V Working
> TI UltraSparc I Working
> TI UltraSparc II Working
> TI UltraSparc IIi Working
> TI UltraSparc IIe Exception 0x28 (division_by_zero) in init_tick_ops
> Can make it to work if is_hummingbird() is changed
> to return 0. The IO stick, and OpenBios stick properties
> are absent, so we have to default to %tick for now.
>
> Sun UltraSparc III Illegal instruction in cheetah_boot():
> wr %g0, %g1, %dcr
> It appears dispatch control register is not implemented.
>
> Sun UltraSparc IIIi
> Sun UltraSparc IV
> Sun UltraSparc IV+
> Sun UltraSparc IIIi+
> In these four CPUs, I am getting exception 0x32 in
> cheetah_generic_boot: stxa %g0, [ %g3 ] #ASI_DMMU
The UltraSPARC III {,i,i+} and IV(+) MMUs are not implemented. IIi is
the best for the sun4u target, I think.
> Sun UltraSparc T1
> Sun UltraSparc T2
Same here. T2 is pretty much a stub currently. The emulation uses the
same MMU as for T1.
> Both of the above boot pretty far but fail in this function when tmpfs is
> mounted:
> direct_pcr_write(unsigned long reg_num, u64 val)
> __asm__ __volatile__("wr %0, 0x0, %%pcr" : : "r" (val));
>
> Seems like performance counter registers are not supported.
Correct. As discussed off-list they are not.
Btw, you can try to get through even without modifying qemu.
Start qemu-system-sparc64 with -s -S options, connect to it with gdb,
set a breakpoint before the instruction and skip it by modifying the
%pc and %npc registers.
> needed to add these to kernel parameters:
> keep_bootcon -> to see where we are panicking
> lpj=1000 -> jiffers could not calculate for some reason.
>
> NEC UltraSparc I Working
>
> Does this look right or may be I have missed something, and we can get some
> of the Sun UltraSparc to work for example?
>
> Thank you,
> Pasha
>
--
Regards,
Artyom Tarasenko
SPARC and PPC PReP under qemu blog: http://tyom.blogspot.com/search/label/qemu
