Richard Henderson <[email protected]> writes:
> On 12/05/2016 03:25 AM, Nikunj A Dadhania wrote:
>> + getVSR(xt_num, &xt, env);
>> + if (msr_le) {
>> + for (i = 0; i < end; i++) {
>> + cpu_stb_data_ra(env, addr, xt.u8[i], GETPC());
>> + addr = addr_add(env, addr, 1);
>> + }
>> + } else {
>> + for (i = 15; i > 15 - end; i--) {
>> + cpu_stb_data_ra(env, addr, xt.u8[i], GETPC());
>> + addr = addr_add(env, addr, 1);
>> + }
>> + }
>
> Have you accidentally swapped the implementations of stxvl and stxvll?
Now I am in doubt :-)
Let me put my understanding here.
In case of stxvl if we have following vector:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
BE |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
LE |00|00|“T”|“S”|“E”|“T”|“ ”|“a”|“ ”|“s”|“i”|“ ”|“s”|“i”|"h"|"T"|
+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
So for LE/BE: u[0] = "T", u[1] = "h", u[2] = "i", u[3] = "s", ....
Storage should be of following order:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
While in case of stxvll
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
BE/LE |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
For LE: u[0] = 0, u[1] = 0, u[2] = "T", u[3] = "S", ....
For BE: u[0] = "T", u[1] = "h", u[2]="i", u[3]="s", ....
Storage should be of following order:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Please let me know your thoughts.
While discussing here with Bharata, I think I will need to handle host
endian here?
Regards,
Nikunj
