On 23 November 2016 at 12:39, <[email protected]> wrote: > From: Vijaya Kumar K <[email protected]> > > Save and Restore ICC_SRE_EL1 register. ICC_SRE_EL1 register > value is used by kernel to check if SRE bit is set or not. > > Signed-off-by: Vijaya Kumar K <[email protected]> > --- > hw/intc/arm_gicv3_kvm.c | 4 ++++ > include/hw/intc/arm_gicv3_common.h | 1 + > 2 files changed, 5 insertions(+) > > diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c > index a317fbf..77af32d 100644 > --- a/hw/intc/arm_gicv3_kvm.c > +++ b/hw/intc/arm_gicv3_kvm.c > @@ -65,6 +65,8 @@ > KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 3) > #define ICC_CTLR_EL1 \ > KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 4) > +#define ICC_SRE_EL1 \ > + KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 5) > #define ICC_IGRPEN0_EL1 \ > KVM_DEV_ARM_VGIC_SYSREG(3, 0, 12, 12, 6) > #define ICC_IGRPEN1_EL1 \ > @@ -404,6 +406,7 @@ static void kvm_arm_gicv3_put(GICv3State *s) > GICv3CPUState *c = &s->cpu[ncpu]; > int num_pri_bits; > > + kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, true); > kvm_gicc_access(s, ICC_CTLR_EL1, ncpu, > &c->icc_ctlr_el1[GICV3_NS], true); > kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu, > @@ -557,6 +560,7 @@ static void kvm_arm_gicv3_get(GICv3State *s) > GICv3CPUState *c = &s->cpu[ncpu]; > int num_pri_bits; > > + kvm_gicc_access(s, ICC_SRE_EL1, ncpu, &c->icc_sre_el1, false); > kvm_gicc_access(s, ICC_CTLR_EL1, ncpu, > &c->icc_ctlr_el1[GICV3_NS], false); > kvm_gicc_access(s, ICC_IGRPEN0_EL1, ncpu, > diff --git a/include/hw/intc/arm_gicv3_common.h > b/include/hw/intc/arm_gicv3_common.h > index 341a311..183c7f8 100644 > --- a/include/hw/intc/arm_gicv3_common.h > +++ b/include/hw/intc/arm_gicv3_common.h > @@ -166,6 +166,7 @@ struct GICv3CPUState { > uint8_t gicr_ipriorityr[GIC_INTERNAL]; > > /* CPU interface */ > + uint64_t icc_sre_el1; > uint64_t icc_ctlr_el1[2]; > uint64_t icc_pmr_el1; > uint64_t icc_bpr[3];
If you're adding a new structure field you must also update the vmstate struct in arm_gicv3_common.c. thanks -- PMM
