Re: [Qemu-devel] [PATCH v2 4/5] target-m68k: Implement bitfield ops for registers

[Laurent Vivier]

Le 09/11/2016 à 14:46, Richard Henderson a écrit :
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
>  target-m68k/translate.c | 210 
> ++++++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 210 insertions(+)
> 
> diff --git a/target-m68k/translate.c b/target-m68k/translate.c
> index 1b3765f..be59c37 100644
> --- a/target-m68k/translate.c
> +++ b/target-m68k/translate.c

> +DISAS_INSN(bfins_reg)
> +{
> +    int ext = read_im16(env, s);
> +    TCGv dst = DREG(insn, 0);
> +    TCGv src = DREG(ext, 12);
> +    int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
> +    int ofs = extract32(ext, 6, 5);  /* big bit-endian */
> +    int pos = 32 - ofs - len;        /* little bit-endian */
> +    TCGv tmp;
> +
> +    tmp = tcg_temp_new();
> +
> +    if (ext & 0x20) {
> +        /* Variable width */
> +        tcg_gen_neg_i32(tmp, DREG(ext, 0));
> +        tcg_gen_andi_i32(tmp, tmp, 31);
> +        tcg_gen_shl_i32(QREG_CC_N, src, tmp);
> +    } else {
> +        /* Immediate width */
> +        tcg_gen_shli_i32(QREG_CC_N, src, 32 - len);
> +    }
> +    set_cc_op(s, CC_OP_LOGIC);
> +
> +    /* Immediate width and offset */
> +    if ((ext & 0x820) == 0) {
> +        /* Check for suitability for deposit.  */
> +        if (pos >= 0) {
> +            tcg_gen_deposit_i32(dst, dst, src, pos, len);
> +        } else {
> +            uint32_t maski = -2U << (len - 1);
> +            uint32_t roti = (ofs + len) & 31;
> +            tcg_gen_andi_i32(tmp, src, maski);

should be:

               tcg_gen_andi_i32(tmp, src, ~maski);

Is it correct?

Thanks,
Laurent