Signed-off-by: Laurent Vivier <laur...@vivier.eu>
---
target-m68k/translate.c | 187 ++++++++++++++++++++++++++++++++++++++++--------
1 file changed, 156 insertions(+), 31 deletions(-)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 461d756..c00978d 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -2348,19 +2348,40 @@ DISAS_INSN(addx_mem)
gen_store(s, opsize, addr_dest, QREG_CC_N);
}
-DISAS_INSN(shift_im)
+static inline void shift_im(DisasContext *s, uint16_t insn, int opsize)
{
- TCGv reg = DREG(insn, 0);
int count = (insn >> 9) & 7;
int logical = insn & 8;
+ int left = insn & 0x100;
+ int bits = opsize_bytes(opsize) * 8;
+ TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical);
if (count == 0) {
count = 8;
}
- if (insn & 0x100) {
- tcg_gen_shri_i32(QREG_CC_C, reg, 31 - count);
+ tcg_gen_movi_i32(QREG_CC_V, 0);
+ if (left) {
+ tcg_gen_shri_i32(QREG_CC_C, reg, bits - count);
tcg_gen_shli_i32(QREG_CC_N, reg, count);
+
+ /* Note that ColdFire always clears V,
+ while M68000 sets if the most significant bit is changed at
+ any time during the shift operation */
+ if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
+ /* if shift count >= bits, V is (reg != 0) */
+ if (count >= bits) {
+ tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, reg, QREG_CC_V);
+ } else {
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ /* mask of sign bit */
+ tcg_gen_sari_i32(t0, reg, 31);
+ tcg_gen_sari_i32(t1, reg, bits - count);
+ tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, t0, t1);
+ }
+ tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
+ }
} else {
tcg_gen_shri_i32(QREG_CC_C, reg, count - 1);
if (logical) {
@@ -2369,29 +2390,26 @@ DISAS_INSN(shift_im)
tcg_gen_sari_i32(QREG_CC_N, reg, count);
}
}
+
+ gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
- /* Note that ColdFire always clears V, while M68000 sets it for
- a change in the sign bit. */
- if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
- tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, reg);
- } else {
- tcg_gen_movi_i32(QREG_CC_V, 0);
- }
-
- tcg_gen_mov_i32(reg, QREG_CC_N);
+ gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N);
set_cc_op(s, CC_OP_FLAGS);
}
-DISAS_INSN(shift_reg)
+static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize)
{
- TCGv reg, s32;
- TCGv_i64 t64, s64;
int logical = insn & 8;
+ int left = insn & 0x100;
+ int bits = opsize_bytes(opsize) * 8;
+ TCGv reg = gen_extend(DREG(insn, 0), opsize, !logical);
+ TCGv s32;
+ TCGv_i64 t64, s64;
+ TCGv zero;
- reg = DREG(insn, 0);
t64 = tcg_temp_new_i64();
s64 = tcg_temp_new_i64();
s32 = tcg_temp_new();
@@ -2402,44 +2420,144 @@ DISAS_INSN(shift_reg)
tcg_gen_andi_i32(s32, DREG(insn, 9), 63);
tcg_gen_extu_i32_i64(s64, s32);
- /* Non-arithmetic shift clears V. Use it as a source zero here. */
- tcg_gen_movi_i32(QREG_CC_V, 0);
+ zero = tcg_const_i32(0);
+ tcg_gen_mov_i32(QREG_CC_V, zero);
- if (insn & 0x100) {
- tcg_gen_extu_i32_i64(t64, reg);
+ tcg_gen_extu_i32_i64(t64, reg);
+ if (left) {
+ tcg_gen_shli_i64(t64, t64, 32 - bits);
tcg_gen_shl_i64(t64, t64, s64);
tcg_temp_free_i64(s64);
tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64);
tcg_temp_free_i64(t64);
+ tcg_gen_sari_i32(QREG_CC_N, QREG_CC_N, 32 - bits);
tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
+
+ /* Note that ColdFire always clears V,
+ while M68000 sets if the most significant bit is changed at
+ any time during the shift operation */
+ if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
+ TCGv t0 = tcg_temp_new();
+ TCGv t1 = tcg_temp_new();
+ TCGv t2 = tcg_const_i32(bits);
+
+ tcg_gen_sub_i32(t2, t2, s32); /* t2 = bits - count */
+
+ tcg_gen_sari_i32(t0, reg, 31);
+ tcg_gen_sar_i32(t1, reg, t2);
+ tcg_temp_free(t2);
+ tcg_gen_setcond_i32(TCG_COND_NE, QREG_CC_V, t0, t1);
+ tcg_temp_free(t1);
+
+ /* if shift count >= bits, V is (reg != 0) */
+ tcg_gen_setcond_i32(TCG_COND_NE, t0, reg, zero);
+ tcg_gen_movcond_i32(TCG_COND_GE, QREG_CC_V, s32, t2, t0,
QREG_CC_V);
+
+ tcg_temp_free(t0);
+
+ tcg_gen_neg_i32(QREG_CC_V, QREG_CC_V);
+
+ /* if shift count is zero, V is 0 */
+ tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_V, s32, zero,
+ QREG_CC_V, zero);
+ }
} else {
- tcg_gen_extu_i32_i64(t64, reg);
- tcg_gen_shli_i64(t64, t64, 32);
+ tcg_gen_shli_i64(t64, t64, 64 - bits);
if (logical) {
+ tcg_gen_shri_i64(t64, t64, 32 - bits);
tcg_gen_shr_i64(t64, t64, s64);
} else {
+ tcg_gen_sari_i64(t64, t64, 32 - bits);
tcg_gen_sar_i64(t64, t64, s64);
}
tcg_temp_free_i64(s64);
tcg_gen_extr_i64_i32(QREG_CC_C, QREG_CC_N, t64);
tcg_temp_free_i64(t64);
+ gen_ext(QREG_CC_N, QREG_CC_N, opsize, 1);
tcg_gen_shri_i32(QREG_CC_C, QREG_CC_C, 31);
}
tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
- /* Note that X = C, but only if the shift count was non-zero. */
- tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V,
+ /* C is cleared if shift count was zero */
+ tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_C, s32, zero,
+ QREG_CC_C, zero);
+
+ /* X = C, but only if the shift count was non-zero. */
+ tcg_gen_movcond_i32(TCG_COND_NE, QREG_CC_X, s32, zero,
QREG_CC_C, QREG_CC_X);
+ tcg_temp_free(zero);
tcg_temp_free(s32);
- /* Note that ColdFire always clears V (which we have done above),
- while M68000 sets it for a change in the sign bit. */
- if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
- tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, reg);
+ /* Write back the result. */
+ gen_partset_reg(opsize, DREG(insn, 0), QREG_CC_N);
+ set_cc_op(s, CC_OP_FLAGS);
+}
+
+DISAS_INSN(shift8_im)
+{
+ shift_im(s, insn, OS_BYTE);
+}
+
+DISAS_INSN(shift16_im)
+{
+ shift_im(s, insn, OS_WORD);
+}
+
+DISAS_INSN(shift_im)
+{
+ shift_im(s, insn, OS_LONG);
+}
+
+DISAS_INSN(shift8_reg)
+{
+ shift_reg(s, insn, OS_BYTE);
+}
+
+DISAS_INSN(shift16_reg)
+{
+ shift_reg(s, insn, OS_WORD);
+}
+
+DISAS_INSN(shift_reg)
+{
+ shift_reg(s, insn, OS_LONG);
+}
+
+DISAS_INSN(shift_mem)
+{
+ int logical = insn & 8;
+ int left = insn & 0x100;
+ TCGv src;
+ TCGv addr;
+
+ SRC_EA(env, src, OS_WORD, !logical, &addr);
+ tcg_gen_movi_i32(QREG_CC_V, 0);
+ if (left) {
+ tcg_gen_shri_i32(QREG_CC_C, src, 15);
+ tcg_gen_shli_i32(QREG_CC_N, src, 1);
+
+ /* Note that ColdFire always clears V,
+ while M68000 sets if the most significant bit is changed at
+ any time during the shift operation */
+ if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
+ src = gen_extend(src, OS_WORD, 1);
+ tcg_gen_xor_i32(QREG_CC_V, QREG_CC_N, src);
+ }
+ } else {
+ tcg_gen_mov_i32(QREG_CC_C, src);
+ if (logical) {
+ tcg_gen_shri_i32(QREG_CC_N, src, 1);
+ } else {
+ tcg_gen_sari_i32(QREG_CC_N, src, 1);
+ }
}
- /* Write back the result. */
- tcg_gen_mov_i32(reg, QREG_CC_N);
+ gen_ext(QREG_CC_N, QREG_CC_N, OS_WORD, 1);
+ tcg_gen_andi_i32(QREG_CC_C, QREG_CC_C, 1);
+ tcg_gen_mov_i32(QREG_CC_Z, QREG_CC_N);
+ tcg_gen_mov_i32(QREG_CC_X, QREG_CC_C);
+
+ DEST_EA(env, insn, OS_WORD, QREG_CC_N, &addr);
set_cc_op(s, CC_OP_FLAGS);
}
@@ -3508,6 +3626,13 @@ void register_m68k_insns (CPUM68KState *env)
INSN(adda, d0c0, f0c0, M68000);
INSN(shift_im, e080, f0f0, CF_ISA_A);
INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
+ INSN(shift8_im, e000, f0f0, M68000);
+ INSN(shift16_im, e040, f0f0, M68000);
+ INSN(shift_im, e080, f0f0, M68000);
+ INSN(shift8_reg, e020, f0f0, M68000);
+ INSN(shift16_reg, e060, f0f0, M68000);
+ INSN(shift_reg, e0a0, f0f0, M68000);
+ INSN(shift_mem, e0c0, fcc0, M68000);
INSN(undef_fpu, f000, f000, CF_ISA_A);
INSN(fpu, f200, ffc0, CF_FPU);
INSN(fbcc, f280, ffc0, CF_FPU);
--
2.7.4
