From: "Gautham R. Shenoy" <[email protected]> vrldmi: Vector Rotate Left Dword then Mask Insert vrlwmi: Vector Rotate Left Word then Mask Insert
Signed-off-by: Gautham R. Shenoy <[email protected]> Signed-off-by: Bharata B Rao <[email protected]> Signed-off-by: Nikunj A Dadhania <[email protected]> --- disas/ppc.c | 2 + target-ppc/helper.h | 2 + target-ppc/int_helper.c | 88 +++++++++++++++++++++++++++++++++++++ target-ppc/translate/vmx-impl.inc.c | 6 +++ target-ppc/translate/vmx-ops.inc.c | 4 +- 5 files changed, 100 insertions(+), 2 deletions(-) diff --git a/disas/ppc.c b/disas/ppc.c index 052cebe..32f0d8d 100644 --- a/disas/ppc.c +++ b/disas/ppc.c @@ -2286,6 +2286,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "vrlh", VX(4, 68), VX_MASK, PPCVEC, { VD, VA, VB } }, { "vrlw", VX(4, 132), VX_MASK, PPCVEC, { VD, VA, VB } }, { "vrsqrtefp", VX(4, 330), VX_MASK, PPCVEC, { VD, VB } }, +{ "vrldmi", VX(4, 197), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "vrlwmi", VX(4, 133), VX_MASK, PPCVEC, { VD, VA, VB} }, { "vsel", VXA(4, 42), VXA_MASK, PPCVEC, { VD, VA, VB, VC } }, { "vsl", VX(4, 452), VX_MASK, PPCVEC, { VD, VA, VB } }, { "vslb", VX(4, 260), VX_MASK, PPCVEC, { VD, VA, VB } }, diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 0337292..9fb8f0d 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -325,6 +325,8 @@ DEF_HELPER_4(vmaxfp, void, env, avr, avr, avr) DEF_HELPER_4(vminfp, void, env, avr, avr, avr) DEF_HELPER_3(vrefp, void, env, avr, avr) DEF_HELPER_3(vrsqrtefp, void, env, avr, avr) +DEF_HELPER_3(vrlwmi, void, avr, avr, avr) +DEF_HELPER_3(vrldmi, void, avr, avr, avr) DEF_HELPER_5(vmaddfp, void, env, avr, avr, avr, avr) DEF_HELPER_5(vnmsubfp, void, env, avr, avr, avr, avr) DEF_HELPER_3(vexptefp, void, env, avr, avr) diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c index dca4798..2273872 100644 --- a/target-ppc/int_helper.c +++ b/target-ppc/int_helper.c @@ -1717,6 +1717,94 @@ void helper_vrsqrtefp(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *b) } } +#define EXTRACT_BITS(size) \ +static inline uint##size##_t extract_bits_u##size(uint##size##_t reg, \ + uint##size##_t start, \ + uint##size##_t end) \ +{ \ + uint##size##_t nr_mask_bits = end - start + 1; \ + uint##size##_t val = 1; \ + uint##size##_t mask = (val << nr_mask_bits) - 1; \ + uint##size##_t shifted_reg = reg >> ((size - 1) - end); \ + return shifted_reg & mask; \ +} + +EXTRACT_BITS(64); +EXTRACT_BITS(32); + +#define MASK(size, max_val) \ +static inline uint##size##_t mask_u##size(uint##size##_t start, \ + uint##size##_t end) \ +{ \ + uint##size##_t ret, max_bit = size - 1; \ + \ + if (likely(start == 0)) { \ + ret = max_val << (max_bit - end); \ + } else if (likely(end == max_bit)) { \ + ret = max_val >> start; \ + } else { \ + ret = (((uint##size##_t)(-1ULL)) >> (start)) ^ \ + (((uint##size##_t)(-1ULL) >> (end)) >> 1); \ + if (unlikely(start > end)) { \ + return ~ret; \ + } \ + } \ + \ + return ret; \ +} + +MASK(32, UINT32_MAX); +MASK(64, UINT64_MAX); + +#define LEFT_ROTATE(size) \ +static inline uint##size##_t left_rotate_u##size(uint##size##_t val, \ + uint##size##_t shift) \ +{ \ + if (!shift) { \ + return val; \ + } \ + \ + uint##size##_t left_val = extract_bits_u##size(val, 0, shift - 1); \ + uint##size##_t right_val = val & mask_u##size(shift, size - 1); \ + \ + return right_val << shift | left_val; \ +} + +LEFT_ROTATE(32); +LEFT_ROTATE(64); + +#define VRLMI(name, size, element, \ + begin_first, begin_last, \ + end_first, end_last, \ + shift_first, shift_last) \ +void helper_##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \ +{ \ + int i; \ + for (i = 0; i < ARRAY_SIZE(r->element); i++) { \ + uint##size##_t src1 = a->element[i]; \ + uint##size##_t src2 = b->element[i]; \ + uint##size##_t src3 = r->element[i]; \ + uint##size##_t begin, end, shift, mask, rot_val; \ + \ + begin = extract_bits_u##size(src2, begin_first, begin_last);\ + end = extract_bits_u##size(src2, end_first, end_last); \ + shift = extract_bits_u##size(src2, shift_first, shift_last);\ + rot_val = left_rotate_u##size(src1, shift); \ + mask = mask_u##size(begin, end); \ + r->element[i] = (rot_val & mask) | (src3 & ~mask); \ + } \ +} + +VRLMI(vrldmi, 64, u64, + 42, 47, /* begin_first, begin_last */ + 50, 55, /* end_first, end_last */ + 58, 63); /* shift_first, shift_last */ + +VRLMI(vrlwmi, 32, u32, + 11, 15, /* begin_first, begin_last */ + 19, 23, /* end_first, end_last */ + 27, 31); /* shift_first, shift_last */ + void helper_vsel(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) { diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c index fc612d9..fdfbd6a 100644 --- a/target-ppc/translate/vmx-impl.inc.c +++ b/target-ppc/translate/vmx-impl.inc.c @@ -488,7 +488,13 @@ GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \ GEN_VXFORM(vrlb, 2, 0); GEN_VXFORM(vrlh, 2, 1); GEN_VXFORM(vrlw, 2, 2); +GEN_VXFORM(vrlwmi, 2, 2); +GEN_VXFORM_DUAL(vrlw, PPC_ALTIVEC, PPC_NONE, \ + vrlwmi, PPC_NONE, PPC2_ISA300) GEN_VXFORM(vrld, 2, 3); +GEN_VXFORM(vrldmi, 2, 3); +GEN_VXFORM_DUAL(vrld, PPC_NONE, PPC2_ALTIVEC_207, \ + vrldmi, PPC_NONE, PPC2_ISA300) GEN_VXFORM(vsl, 2, 7); GEN_VXFORM(vsr, 2, 11); GEN_VXFORM_ENV(vpkuhum, 7, 0); diff --git a/target-ppc/translate/vmx-ops.inc.c b/target-ppc/translate/vmx-ops.inc.c index cc7ed7e..76b3593 100644 --- a/target-ppc/translate/vmx-ops.inc.c +++ b/target-ppc/translate/vmx-ops.inc.c @@ -143,8 +143,8 @@ GEN_VXFORM_207(vsubcuq, 0, 21), GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207), GEN_VXFORM(vrlb, 2, 0), GEN_VXFORM(vrlh, 2, 1), -GEN_VXFORM(vrlw, 2, 2), -GEN_VXFORM_207(vrld, 2, 3), +GEN_VXFORM_DUAL(vrlw, vrlwmi, 2, 2, PPC_ALTIVEC, PPC_NONE), +GEN_VXFORM_DUAL(vrld, vrldmi, 2, 3, PPC_NONE, PPC2_ALTIVEC_207), GEN_VXFORM(vsl, 2, 7), GEN_VXFORM(vsr, 2, 11), GEN_VXFORM(vpkuhum, 7, 0), -- 2.7.4
