The two main goals in this patch set are:
* Make use of the new MO_ALIGN_* flags, to allow less use of
check_align, and support partially misaligned fp memory ops.
* More cleanups for ASIs, in the end using the new atomic ops.
The final two patches require the "cmpxchg atomic" v5 patch set
which I posted yesterday. Otherwise this patch set should apply
to master. The full tree is at
git://github.com/rth7680/qemu.git tgt-sparc-6
There is overlap with Artyom's sun4v patch set.
* MMU_PHYS_IDX cleans up patch 14 (use direct address translation
in hyperprivleged mode). And if I read patch 9 correctly, may
allow MMU_HYPV_IDX to be redundant with MMU_PHYS_IDX. Which would
be nice, because 7 or more mmu idxes causes the sizes of each of
the tlb's to be reduced.
* The patches that touch the asi's will probably conflict.
r~
Richard Henderson (16):
target-sparc: Use overalignment flags for twinx and block asis
target-sparc: Introduce cpu_raise_exception_ra
target-sparc: Add MMU_PHYS_IDX
target-sparc: Use MMU_PHYS_IDX for bypass asis
target-sparc: Handle more twinx asis
target-sparc: Implement swap_asi inline
target-sparc: Implement ldstub_asi inline
target-sparc: Implement cas_asi/casx_asi inline
target-sparc: Implement BCOPY/BFILL inline
target-sparc: Remove asi helper code handled inline
target-sparc: Implement ldqf and stqf inline
target-sparc: Allow 4-byte alignment on fp mem ops
target-sparc: Remove MMU_MODE*_SUFFIX
target-sparc: Optmize writeback of cpu_cond
target-sparc: Use tcg_gen_atomic_xchg_tl
target-sparc: Use tcg_gen_atomic_cmpxchg_tl
target-sparc/cpu.h | 34 +-
target-sparc/helper.c | 52 ++-
target-sparc/helper.h | 7 -
target-sparc/ldst_helper.c | 998 ++++++++-------------------------------------
target-sparc/mmu_helper.c | 47 ++-
target-sparc/translate.c | 446 ++++++++++++--------
target-sparc/win_helper.c | 37 +-
7 files changed, 522 insertions(+), 1099 deletions(-)
--
2.7.4
