On Mon, Sep 26, 2016 at 01:52:22PM +0000, Paul Kennedy wrote: > From 7bf015d76a5b53cd061c91f91fea4427101b26fd Mon Sep 17 00:00:00 2001 > From: Paul Kennedy <[email protected]> > Date: Mon, 26 Sep 2016 11:59:00 +0100 > Subject: [PATCH] arm-smmu: Fix bug when merging two 32 bit words to form 64 > bit word > > Fix bug where least significant 32 bits overwrite most significant > 32 bits of TTBR1 register.
Hi Paul, Thanks for the patch. This code is not upstream yet, it's staged in the Xilinx tree. It probably doesn't makes sense to CC [email protected] and [email protected] yet but there's a [email protected] for future patches to staged Xilinx code. Reviewed-by: Edgar E. Iglesias <[email protected]> Alistair, can you merge this to our trees? Cheers, Edgar > > Signed-off-by: Paul C Kennedy <[email protected]> > --- > hw/misc/arm-smmu.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/hw/misc/arm-smmu.c b/hw/misc/arm-smmu.c > index 7e7acd8..8255f3e 100644 > --- a/hw/misc/arm-smmu.c > +++ b/hw/misc/arm-smmu.c > @@ -6566,7 +6566,7 @@ static bool smmu500_at64(SMMU *s, unsigned int cb, > hwaddr va, > > req.ttbr[1][1] = s->regs[R_SMMU_CB0_TTBR1_HIGH + cb_offset]; > req.ttbr[1][1] <<= 32; > - req.ttbr[1][1] = s->regs[R_SMMU_CB0_TTBR1_LOW + cb_offset]; > + req.ttbr[1][1] |= s->regs[R_SMMU_CB0_TTBR1_LOW + cb_offset]; > > if (req.s2_enabled) { > req.tcr[2] = s->regs[R_SMMU_CB0_TCR_LPAE + cb2_offset]; > -- > 1.7.9.5 >
