Re: [Qemu-devel] [PATCH 03/18] target-riscv: Add initialization for translation

[Richard Henderson]

On 09/26/2016 03:56 AM, Sagar Karandikar wrote:
 RISCVCPU *cpu_riscv_init(const char *cpu_model)
 {
-    return NULL;
+    RISCVCPU *cpu;
+    CPURISCVState *env;
+    const riscv_def_t *def;
+
+    def = cpu_riscv_find_by_name(cpu_model);
+    if (!def) {
+        return NULL;
+    }
+    cpu = RISCV_CPU(object_new(TYPE_RISCV_CPU));
+    env = &cpu->env;
+    env->cpu_model = def;
+
+    memset(env->csr, 0, 4096 * sizeof(target_ulong));

sizeof(env->csr)?

And besides that, doesn't this more properly belong in a reset function, where 
that memset will already have been done?

+    env->priv = PRV_M;
+
+    /* set mcpuid from def */
+    env->csr[CSR_MISA] = def->init_misa_reg;
+    object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
+
+    /* fpu flags: */
+    set_default_nan_mode(1, &env->fp_status);