From: Sergey Sorokin <[email protected]> If an alignment fault occurred and target EL is using AArch32, then DFSR/IFSR bit LPAE[9] must be set correctly.
Signed-off-by: Sergey Sorokin <[email protected]> Message-id: [email protected] Reviewed-by: Peter Maydell <[email protected]> Signed-off-by: Peter Maydell <[email protected]> --- target-arm/op_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c index 3e8588e..be27b21 100644 --- a/target-arm/op_helper.c +++ b/target-arm/op_helper.c @@ -194,7 +194,7 @@ void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, * the LPAE long descriptor format, or the short descriptor format */ if (arm_s1_regime_using_lpae_format(env, cpu_mmu_index(env, false))) { - env->exception.fsr = 0x21; + env->exception.fsr = (1 << 9) | 0x21; } else { env->exception.fsr = 0x1; } -- 2.7.4
