On 21 June 2016 at 18:28, Pranith Kumar <[email protected]> wrote: > Reg. the second point, I did consider this situation of running x86 on > ARM where such barriers are necessary for correctness. But, I am > really apprehensive of the cost it will impose. I am not sure if there > are any alternative solutions to avoid generating barriers for each > memory operation, but it would be great if we could reduce them.
I vaguely recall an idea that you could avoid needing explicit barriers by turning all the guest load/stores into host load-acquire/store-release, but I have no idea whether that's (a) actually true (b) any better than piles of explicit barriers. thanks -- PMM
