On 16 March 2016 at 23:40, Andrew Baumann <[email protected]> wrote: > Yes, that should work. Bits 0 and 3 are wired up to what qemu refers to as > GTIMER_PHYS and GTIMER_VIRT respectively. (The other two timers aren't > currently connected; I can't remember if that's because they weren't > modelled by core QEMU when I was implementing the device model, or just > because I wasn't sure how to route them and never came back to fix it.)
Probably we hadn't got round to modelling the other two timers yet. You want GTIMER_PHYS -> cntpnsirq GTIMER_VIRT -> cntvirq GTIMER_HYP -> cnthpirq GTIMER_SEC -> cntpsirq Currently we have the virt timer wired up right but we've connected the phys timer to the secure-phys-timer interrupt line, which will be why it doesn't appear to work. The code in hw/arm/bcm2836.c:bcm2836_realize() needs fixing. thanks -- PMM
