On 03/01/2016 07:12 AM, Paolo Bonzini wrote:
> SMSW and LMSW accept register operands, but commit 1906b2a ("target-i386:
> Rearrange processing of 0F 01", 2016-02-13) did not account for that.
>
> Fixes: 1906b2af7c2345037d9b2fdf484b457b5acd09d1
> Cc: [email protected]
> Reported-by: Hervé Poussineau <[email protected]>
> Signed-off-by: Paolo Bonzini <[email protected]>
> ---
> target-i386/translate.c | 38 ++++++++++++++++++++++----------------
> 1 file changed, 22 insertions(+), 16 deletions(-)
Reviewed-by: Richard Henderson <[email protected]>
Sorry about that. As recompense, I just noticed that we're not implementing
these instructions properly for 64-bit mode. I'll post a patch for that as
well.
r~
