Now that the spapr code has been extended to support 64kiB pages, we can
allow guests to use 64kiB pages on an emulated POWER8 by adding it to the
"segment_page_sizes" structure which is advertised via the device tree.
For now we just add support for 64kiB pages in 64kiB page segments. Real
POWER8 also supports 64kiB pages in 4kiB page segments, but that will
require more work to implement.
Real POWER7s (and maybe some other CPU models) also support 64kiB pages,
however, I don't want to add support there without double checking if they
use the same HPTE and SLB encodings (in principle these are implementation
dependent).
Signed-off-by: David Gibson <da...@gibson.dropbear.id.au>
---
target-ppc/translate_init.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index e88dc7f..ae5a269 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8200,6 +8200,22 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+ static const struct ppc_segment_page_sizes POWER8_sps = {
+ .sps = {
+ { .page_shift = 12, /* 4K */
+ .slb_enc = 0,
+ .enc = { { .page_shift = 12, .pte_enc = 0 } }
+ },
+ { .page_shift = 16, /* 64K */
+ .slb_enc = 0x110,
+ .enc = { { .page_shift = 16, .pte_enc = 0x1 } }
+ },
+ { .page_shift = 24, /* 16M */
+ .slb_enc = 0x100,
+ .enc = { { .page_shift = 24, .pte_enc = 0 } }
+ },
+ }
+ };
dc->fw_name = "PowerPC,POWER8";
dc->desc = "POWER8";
@@ -8258,6 +8274,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
pcc->l1_dcache_size = 0x8000;
pcc->l1_icache_size = 0x8000;
pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
+ pcc->sps = &POWER8_sps;
}
#endif /* defined (TARGET_PPC64) */
--
2.5.0
