Still there in the latest master. To clarify, running the binary with the -cpu athlon switch (same instruction set as P3) also exhibits the problem whereas a real athlon SIGILL's correctly.
** Description changed: Running a binary containing a movsd instruction (SSE2) in 32-bit - qemu-i386 -cpu pentium3 from 20150609 results in flawless execution - whereas it should crash with SIGILL as P3 only had SSE. + qemu-i386 from 20150609 using the -cpu pentium3 switch results in + flawless execution whereas it should crash with SIGILL as P3 only had + SSE and not SSE2. ** Summary changed: - qemu-i386 pentium3 incorrect instruction set + qemu-i386 pentium3/athlon incorrect instruction set -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1469342 Title: qemu-i386 pentium3/athlon incorrect instruction set Status in QEMU: New Bug description: Running a binary containing a movsd instruction (SSE2) in 32-bit qemu-i386 from 20150609 using the -cpu pentium3 switch results in flawless execution whereas it should crash with SIGILL as P3 only had SSE and not SSE2. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1469342/+subscriptions
