The patchset implements the latest microMIPS32 Release 6 Instruction Set. However LLX, LLXE, SCX and SCXE aren't included in the patchset.
For more information, microMIPS R6 Instruction Set document is available: MIPS Architecture for Programmers Volume II-B: microMIPS32 Instruction Set Revision 6.01 http://www.imgtec.com/mips/architectures/mips32.asp Yongbok Kim (13): target-mips: fix {D,W}RGPR in microMIPS target-mips: add microMIPS TLBINV, TLBINVF target-mips: refactor {D}LSA, {D}ALIGN, {D}BITSWAP target-mips: rearrange gen_compute_compact_branch target-mips: signal RI for removed instructions in microMIPS R6 target-mips: add microMIPS32 R6 opcode enum target-mips: microMIPS32 R6 branches and jumps target-mips: microMIPS32 R6 POOL32A{XF} instructions target-mips: microMIPS32 R6 POOL32F instructions target-mips: microMIPS32 R6 POOL32{I,C} instructions target-mips: microMIPS32 R6 Major instructions target-mips: microMIPS32 R6 POOL16{A,C} instructions target-mips: add mips32r6-generic CPU definition target-mips/translate.c | 2027 +++++++++++++++++++++++++++++------------- target-mips/translate_init.c | 37 + 2 files changed, 1434 insertions(+), 630 deletions(-) -- 1.7.5.4
