Status.FR bit must be ignored on write and read as 1 when an implementation of Release 6 of the Architecture in which a 64-bit floating point unit is implemented.
Signed-off-by: Leon Alrae <[email protected]> --- v3: * remove line modifying CP0_Status_rw_bitmask as this is done while defining CPU --- target-mips/translate.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index a804322..7cfda3d 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -17942,6 +17942,12 @@ void cpu_state_reset(CPUMIPSState *env) } } #endif + if ((env->insn_flags & ISA_MIPS32R6) && + (env->active_fpu.fcr0 & (1 << FCR0_F64))) { + /* Status.FR = 0 mode in 64-bit FPU not allowed in R6 */ + env->CP0_Status |= (1 << CP0St_FR); + } + compute_hflags(env); cs->exception_index = EXCP_NONE; } -- 1.7.5.4
