Am 02.05.2014 16:33, schrieb Paolo Bonzini: > Most MSRs, plus the FPU, MMX, MXCSR, XMM and YMM registers should not > be zeroed on INIT (Table 9-1 in the Intel SDM). Copy them out of > CPUX86State and back in, instead of special casing env->pat. > > The relevant fields are already consecutive except PAT and SMBASE. > However: > > - KVM and Hyper-V MSRs should be reset because they include memory > locations written by the hypervisor. These MSRs are moved together > at the end of the preserved area. > > - SVM state can be moved out of the way since it is written by VMRUN. > > Cc: Andreas Färber <[email protected]> > Signed-off-by: Paolo Bonzini <[email protected]> > --- > target-i386/cpu.c | 3 +-- > target-i386/cpu.h | 42 ++++++++++++++++++++++++++---------------- > target-i386/helper.c | 10 ++++++++-- > 3 files changed, 35 insertions(+), 20 deletions(-)
Fine with me. You might as well use a third marker for zeroed-on-reset to avoid the pat -> cpuid_level change. If we want to widen this pattern, a macro might make sense. Regards, Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
