Hi,
I am a user of qemu. I found that in qemu2.0.0-rc0 the gic model was
updated. However, it seems loss ability to bind irqs to any specified core when
the board includes multiple cortex-a9 cores. The problematic codes maybe locate
at hw/intc/arm_gic.c:
50 void gic_update(GICState *s)
...
68 for (irq = 0; irq < s->num_irq; irq++) {
69 if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm)) {
70 if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
71 best_prio = GIC_GET_PRIORITY(irq, cpu);
72 best_irq = irq;
73 }
74 }
75 }
...
gic_test_pending checks if the pending bits of an irq are set. I think the
pending bits reflect core bindings according to the func "gic_set_irq". But in
the following codes:
115 static void gic_set_irq_generic(GICState *s, int irq, int level,
116 int cm, int target)
117 {
118 if (level) {
119 GIC_SET_LEVEL(irq, cm);
120 DPRINTF("Set %d pending mask %x\n", irq, target);
121 if (GIC_TEST_EDGE_TRIGGER(irq)) {
122 GIC_SET_PENDING(irq, target);
123 }
124 } else {
125 GIC_CLEAR_LEVEL(irq, cm);
126 }
127 }
if level trigger the core target parameter of the irq is ignored and its
pending bits will not be set. So how does the core target parameter make its
affect?
I regard it as a bug because in previous version (1.5), our kernel and gic work
well.
Would anyone consider about this question?
thanks
Xiaodong Zhu
