On Sat, Mar 29, 2014 at 2:09 AM, Peter Maydell <[email protected]> wrote:
> From: Rob Herring <[email protected]>
>
> Set up the required syndrome information when we detect an MMU fault.
>
> Signed-off-by: Rob Herring <[email protected]>
> [PMM: split out from exception handling patch, tweaked to bring
> in line with how we create other kinds of syndrome information]
> Signed-off-by: Peter Maydell <[email protected]>
> ---
> target-arm/helper.c | 12 ++++++++++++
> target-arm/internals.h | 13 +++++++++++++
> 2 files changed, 25 insertions(+)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index fe642df..9866e50 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -3696,6 +3696,8 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr
> address,
> target_ulong page_size;
> int prot;
> int ret, is_user;
> + uint32_t syn;
> + bool same_el = (arm_current_pl(env) != 0);
>
> is_user = mmu_idx == MMU_USER_IDX;
> ret = get_phys_addr(env, address, access_type, is_user, &phys_addr,
> &prot,
> @@ -3708,14 +3710,24 @@ int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr
> address,
> return 0;
> }
>
> + /* AArch64 syndrome does not have an LPAE bit */
> + syn = ret & ~(1 << 9);
> +
> + /* For insn and data aborts we assume there is no instruction syndrome
> + * information; this is always true for exceptions reported to EL1.
> + */
> if (access_type == 2) {
> + syn = syn_insn_abort(same_el, 0, 0, syn);
> cs->exception_index = EXCP_PREFETCH_ABORT;
> } else {
> + syn = syn_data_abort(same_el, 0, 0, 0, access_type == 1, syn);
> if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) {
> ret |= (1 << 11);
> }
> cs->exception_index = EXCP_DATA_ABORT;
> }
> +
> + env->exception.syndrome = syn;
> env->exception.vaddress = address;
> env->exception.fsr = ret;
> return 1;
> diff --git a/target-arm/internals.h b/target-arm/internals.h
> index 0300ba3..e8d98a1 100644
> --- a/target-arm/internals.h
> +++ b/target-arm/internals.h
> @@ -188,4 +188,17 @@ static inline uint32_t syn_cp15_rrt_trap(int cv, int
> cond, int opc1, int crm,
> | (rt2 << 10) | (rt << 5) | (crm << 1) | isread;
> }
>
> +static inline uint32_t syn_insn_abort(bool same_el, int ea, int s1ptw, int
> fsc)
Why the mix of bools and ints for the 1 bit fields?
Regards,
Peter
> +{
> + return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
> + | (ea << 9) | (s1ptw << 7) | fsc;
> +}
> +
> +static inline uint32_t syn_data_abort(bool same_el, int ea, int cm, int
> s1ptw,
> + int wnr, int fsc)
> +{
> + return (EC_DATAABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
> + | (ea << 9) | (cm << 8) | (s1ptw << 7) | (wnr << 6) | fsc;
> +}
> +
> #endif
> --
> 1.9.0
>
>
