Hi; this is the target-arm queue for 2.0rc1. It looks
pretty big but most of it is the last big dose of Neon
A64 instructions which are pretty safe changes.
I'm currently expecting that I'll send another pullreq
either last minute before rc1 or after rc1, because
these things are still in the pipeline:
* pl011 bugfixes for intermittent serial port hangs
* the last 4 A64 Neon insns
(If anybody thinks there's something else that should
be on that list now would be a good time to remind me :-))
thanks
-- PMM
The following changes since commit 87f639629334c4592c3ba1011af0f691db1e7ed1:
Merge remote-tracking branch 'remotes/kraxel/tags/pull-gtk-3' into staging
(2014-03-17 15:51:57 +0000)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20140317
for you to fetch changes up to 1ed27a17cd9d9ebec8963bc358d74060b1dd6127:
scripts/qemu-binfmt-conf.sh: Add AArch64 registration (2014-03-17 16:31:53
+0000)
----------------------------------------------------------------
target-arm queue:
* more A64 Neon instructions
* fixes to reset CBAR values for A9 and A15 boards
* fix accesses to PMCR register in -icount mode
----------------------------------------------------------------
Alex Bennée (11):
target-arm: A64: Fix bug in add_sub_ext handling of rn
target-arm: A64: Add last AdvSIMD Integer to FP ops
target-arm: A64: Add FSQRT to C3.6.17 (two misc)
target-arm: A64: Add remaining CLS/Z vector ops
target-arm: A64: Saturating and narrowing shift ops
target-arm: A64: Add FRECPX (reciprocal exponent)
softfloat: export squash_input_denormal functions
target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE,
FRECPE
target-arm: A64: Move handle_2misc_narrow function
target-arm: A64: Implement scalar saturating narrow ops
target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)
Peter Maydell (19):
vexpress: Set reset-cbar property for CPUs
realview-pbx-a9: Set reset-cbar property for CPUs
exynos4210: Set reset-cbar property of Cortex-A9 CPUs
virt: Set reset-cbar on CPUs
target-arm: Add ARM_CP_IO notation to PMCR reginfo
target-arm: A64: Implement PMULL instruction
target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP
target-arm: A64: Implement SHLL, SHLL2
target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions
target-arm: A64: Implement FCVTN
target-arm: A64: Implement FCVTL
target-arm: A64: List unsupported shift-imm opcodes
target-arm: A64: Implement SRI
target-arm: A64: Implement FRINT*
exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder
target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL
target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories
target-arm: A64: Implement FCVTXN
scripts/qemu-binfmt-conf.sh: Add AArch64 registration
fpu/softfloat.c | 4 +-
hw/arm/exynos4210.c | 16 +-
hw/arm/realview.c | 39 +-
hw/arm/vexpress.c | 123 ++--
hw/arm/virt.c | 6 +
include/exec/exec-all.h | 2 +-
include/fpu/softfloat.h | 7 +
scripts/qemu-binfmt-conf.sh | 3 +
target-arm/helper-a64.c | 178 ++++++
target-arm/helper-a64.h | 10 +
target-arm/helper.c | 332 ++++++++--
target-arm/helper.h | 10 +-
target-arm/translate-a64.c | 1411 ++++++++++++++++++++++++++++++++++++++-----
target-arm/translate.c | 25 +-
target-arm/translate.h | 6 +
15 files changed, 1882 insertions(+), 290 deletions(-)
