Hi. This is a second version of the A64 Neon patchset six
which I sent out a little while back. Changes:
* fixed the 'hunk in wrong patch' snafu
* adjusted FCVTN to pass 'size - 1' to handle_2misc_narrow;
this puts it in line with other callers and means the
function always takes the size of destination element
* added more patches on the end, implementing
+ SQSHL, SQSHLU, UQSHL
+ FCVTZS, FCVTZU
+ URECPE, FRECPE
+ SQXTN, SQXTUN, UQXTN in s2misc
+ FCVTXN
+ URSQRTE, FRSQRTE
This means the only unimplemented instructions are:
SUQADD, USQADD, SQABS, SQNEG. (We're working on those but
they didn't quite make it and I wanted to send this
series out today.)
NOTE: I intend to get these patches in for rc1, so will
be putting them into a pull request in time for the 19th
(Wednesday) in the absence of review issues.
The (trivial) softfloat patch is provided under the
softfloat 2a or 2b license at your option.
thanks
-- PMM
Alex Bennée (11):
target-arm: A64: Fix bug in add_sub_ext handling of rn
target-arm: A64: Add last AdvSIMD Integer to FP ops
target-arm: A64: Add FSQRT to C3.6.17 (two misc)
target-arm: A64: Add remaining CLS/Z vector ops
target-arm: A64: Saturating and narrowing shift ops
target-arm: A64: Add FRECPX (reciprocal exponent)
softfloat: export squash_input_denormal functions
target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE,
FRECPE
target-arm: A64: Move handle_2misc_narrow function
target-arm: A64: Implement scalar saturating narrow ops
target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)
Peter Maydell (14):
target-arm: A64: Implement PMULL instruction
target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP
target-arm: A64: Implement SHLL, SHLL2
target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions
target-arm: A64: Implement FCVTN
target-arm: A64: Implement FCVTL
target-arm: A64: List unsupported shift-imm opcodes
target-arm: A64: Implement SRI
target-arm: A64: Implement FRINT*
exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder
target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL
target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories
target-arm: A64: Implement FCVTXN
scripts/qemu-binfmt-conf.sh: Add AArch64 registration
fpu/softfloat.c | 4 +-
include/exec/exec-all.h | 2 +-
include/fpu/softfloat.h | 7 +
scripts/qemu-binfmt-conf.sh | 3 +
target-arm/helper-a64.c | 178 ++++++
target-arm/helper-a64.h | 10 +
target-arm/helper.c | 331 ++++++++--
target-arm/helper.h | 10 +-
target-arm/translate-a64.c | 1411 ++++++++++++++++++++++++++++++++++++++-----
target-arm/translate.c | 25 +-
target-arm/translate.h | 6 +
11 files changed, 1772 insertions(+), 215 deletions(-)
--
1.9.0
