On 11/28/2013 10:55 AM, Sebastian Huber wrote:
> Hello,
>
> On 2013-11-26 15:04, Sebastian Huber wrote:
>> The LEON3 processor has support for the CASA instruction which is
>> normally only available for SPARC V9 processors. Binutils 2.24
>> and GCC 4.9 will support this instruction for LEON3. GCC uses it to
>> generate C11 atomic operations.
>> ---
>> target-sparc/cpu.c | 3 +-
>> target-sparc/cpu.h | 4 ++-
>> target-sparc/helper.h | 4 ++-
>> target-sparc/ldst_helper.c | 26 +++++++++++++-----------
>> target-sparc/translate.c | 47
>> ++++++++++++++++++++++++++++---------------
>> 5 files changed, 52 insertions(+), 32 deletions(-)
> [...]
>
> this patch doesn't work since the ASI 0x80 used for the synthetic CAS
> instruction is not implemented in helper_ld_asi() for !TARGET_SPARC64.
>
> I tried to add a
>
> case 0x80: /* Primary */
> {
> switch (size) {
> case 1:
> ret = ldub_raw(addr);
> break;
> case 2:
> ret = lduw_raw(addr);
> break;
> case 4:
> ret = ldl_raw(addr);
> break;
> default:
> case 8:
> ret = ldq_raw(addr);
> break;
> }
> }
> break;
>
> but this results in a Qemu segmentation fault.
>
Hello Sebastian,
I missed this email. It's easier for me to see you message if I'm in
copy, also add Blue Swirl <[email protected]> in copy for all SPARC
patches.
ASI 0x80 doesn't make sense in SPARC32 where does this value come from?
I guess it's TCGv_i32 r_asi = tcg_const_i32(GET_FIELD(insn, 19, 26));,
right?
