On 23 January 2014 15:28, Peter Maydell <[email protected]> wrote:
> Add some of the integer operations in the SIMD 3-same group:
> specifically, the comparisons, addition and subtraction.
>
> @@ -6040,7 +6062,141 @@ static void disas_simd_3same_float(DisasContext *s,
> uint32_t insn)
> /* Integer op subgroup of C3.6.16. */
> static void disas_simd_3same_int(DisasContext *s, uint32_t insn)
> {
> - unsupported_encoding(s, insn);
> + int is_q = extract32(insn, 30, 1);
> + int u = extract32(insn, 29, 1);
> + int size = extract32(insn, 22, 2);
> + int opcode = extract32(insn, 11, 5);
> + int rm = extract32(insn, 16, 5);
> + int rn = extract32(insn, 5, 5);
> + int rd = extract32(insn, 0, 5);
> + int pass;
> +
> + switch (opcode) {
> + case 0x13: /* MUL, PMUL */
> + if (u && size != 0) {
> + unallocated_encoding(s);
> + return;
> + }
> + /* fall through */
> + case 0x0: /* SHADD, UHADD */
> + case 0x2: /* SRHADD, URHADD */
> + case 0x4: /* SHSUB, UHSUB */
> + case 0xc: /* SMAX, UMAX */
> + case 0xd: /* SMIN, UMIN */
> + case 0xe: /* SABD, UABD */
> + case 0xf: /* SABA, UABA */
> + case 0x12: /* MLA, MLS */
> + if (size == 3) {
> + unallocated_encoding(s);
> + return;
> + }
> + unsupported_encoding(s, insn);
> + return;
> + case 0x1: /* SQADD */
> + case 0x5: /* SQSUB */
> + case 0x8: /* SSHL, USHL */
> + case 0x9: /* SQSHL, UQSHL */
> + case 0xa: /* SRSHL, URSHL */
> + case 0xb: /* SQRSHL, UQRSHL */
> + if (size == 3 && !is_q) {
> + unallocated_encoding(s);
> + return;
> + }
> + unsupported_encoding(s, insn);
> + return;
> + default:
> + if (size == 3 && !is_q) {
> + unallocated_encoding(s);
> + return;
> + }
> + break;
> + }
Just noticed this switch is missing a case:
case 0x16: /* SQDMULH, SQRDMULH */
if (size == 0 || size == 3) {
unallocated_encoding(s);
return;
}
break;
thanks
-- PMM
