On Mon, 2014-01-20 at 00:44 +0100, Alexander Graf wrote: > In addition to the L1 data cache configuration register L1CFG0 there is > also another one for the L1 instruction cache called L1CFG1. > > Emulate that one with the same values as the data one. > > Signed-off-by: Alexander Graf <[email protected]> > --- > target-ppc/cpu.h | 1 + > target-ppc/translate_init.c | 8 +++++++- > 2 files changed, 8 insertions(+), 1 deletion(-) > > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index 1289e13..15abad4 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -1367,6 +1367,7 @@ static inline int cpu_mmu_index (CPUPPCState *env) > #define SPR_Exxx_BBEAR (0x201) > #define SPR_Exxx_BBTAR (0x202) > #define SPR_Exxx_L1CFG0 (0x203) > +#define SPR_Exxx_L1CFG1 (0x204) > #define SPR_Exxx_NPIDR (0x205) > #define SPR_ATBL (0x20E) > #define SPR_ATBU (0x20F) > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index 37a0ed2..403ce7a 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -4437,6 +4437,8 @@ static void init_proc_e500 (CPUPPCState *env, int > version) > uint64_t ivpr_mask = 0xFFFF0000ULL; > uint32_t l1cfg0 = 0x3800 /* 8 ways */ > | 0x0020; /* 32 kb */ > + uint32_t l1cfg1 = 0x3800 /* 8 ways */ > + | 0x0020; /* 32 kb */ > #if !defined(CONFIG_USER_ONLY) > int i; > #endif > @@ -4505,6 +4507,7 @@ static void init_proc_e500 (CPUPPCState *env, int > version) > env->dcache_line_size = 64; > env->icache_line_size = 64; > l1cfg0 |= 0x1000000; /* 64 byte cache block size */ > + l1cfg1 |= 0x1000000; /* 64 byte cache block size */ > break; > default: > cpu_abort(env, "Unknown CPU: " TARGET_FMT_lx "\n", > env->spr[SPR_PVR]); > @@ -4555,7 +4558,10 @@ static void init_proc_e500 (CPUPPCState *env, int > version) > SPR_NOACCESS, SPR_NOACCESS, > &spr_read_generic, &spr_write_generic, > l1cfg0); > - /* XXX : not implemented */ > + spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1", > + SPR_NOACCESS, SPR_NOACCESS, > + &spr_read_generic, &spr_write_generic, > + l1cfg1);
LICFGn should be read-only. -Scott
