From: Peter Crosthwaite <[email protected]> This should be rechecked on bus write accesses as such accesses may change the underlying state that generates the interrupt. Particular relevant for when the guest touches the interrupt status or mask.
Signed-off-by: Peter Crosthwaite <[email protected]> Message-id: 1c250cd61b7b8de492fbc8b79b8370958a56d83b.1388626249.git.peter.crosthwa...@xilinx.com Signed-off-by: Peter Maydell <[email protected]> --- hw/char/cadence_uart.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index a7b2f21..fb9db89 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -403,6 +403,7 @@ static void uart_write(void *opaque, hwaddr offset, uart_parameters_setup(s); break; } + uart_update_status(s); } static uint64_t uart_read(void *opaque, hwaddr offset, -- 1.8.5
