On 12/22/2013 03:50 AM, Aurelien Jarno wrote:
> +static inline target_ulong cpu_read_sr(CPUSH4State *env)
> +{
> + return (env->sr & ~(1u << SR_T)) | (env->sr_t << SR_T);
> +}
> +
> +static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
> +{
> + env->sr_t = sr & (1u << SR_T);
> + env->sr = sr & ~(1u << SR_T);
> +}
...
> +static void gen_read_sr(TCGv dst)
> +{
> + tcg_gen_andi_i32(dst, cpu_sr, ~(1u << SR_T));
> + tcg_gen_or_i32(dst, dst, cpu_sr_t);
> +}
> +
> +static void gen_write_sr(TCGv src)
> +{
> + tcg_gen_andi_i32(cpu_sr, src, ~(1u << SR_T));
> + tcg_gen_andi_i32(cpu_sr_t, src, (1u << SR_T));
> +}
If the writer always clears SR_T when assigning to env->sr,
then there's no need to clear it when reading from env->sr.
Or vice versa.
Otherwise,
Reviewed-by: Richard Henderson <r...@twiddle.net>
r~
