This patch adds emulation for the conditional increment (cinc) instruction.
Signed-off-by: Alexander Graf <[email protected]> --- target-arm/helper-a64.c | 34 ++++++++++++++++++++++++++++++++++ target-arm/helper-a64.h | 1 + target-arm/translate-a64.c | 17 +++++++++++++++++ 3 files changed, 52 insertions(+) diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c index 9aaf181..3f055b6 100644 --- a/target-arm/helper-a64.c +++ b/target-arm/helper-a64.c @@ -187,3 +187,37 @@ uint32_t HELPER(cond)(uint32_t pstate, uint32_t cond) return !!r; } + +static int get_bits(uint32_t inst, int start, int len) +{ + return (inst >> start) & ((1 << len) - 1); +} + +uint64_t HELPER(cinc)(uint32_t pstate, uint32_t insn, uint64_t n, uint64_t m) +{ + bool else_inc = get_bits(insn, 10, 1); + int cond = get_bits(insn, 12, 4); + bool else_inv = get_bits(insn, 30, 1); + bool is_32bit = !get_bits(insn, 31, 1); + uint64_t r; + + if (helper_cond(pstate, cond)) { + r = n; + goto out; + } + + r = m; + if (else_inv) { + r = ~r; + } + if (else_inc) { + r++; + } + +out: + if (is_32bit) { + r = (uint32_t)r; + } + + return r; +} diff --git a/target-arm/helper-a64.h b/target-arm/helper-a64.h index 99f4be7..8874518 100644 --- a/target-arm/helper-a64.h +++ b/target-arm/helper-a64.h @@ -23,3 +23,4 @@ DEF_HELPER_FLAGS_4(pstate_sub, TCG_CALL_NO_RWG_SE, i32, i32, i64, i64, i64) DEF_HELPER_FLAGS_4(pstate_sub32, TCG_CALL_NO_RWG_SE, i32, i32, i64, i64, i64) DEF_HELPER_FLAGS_3(sign_extend, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64) DEF_HELPER_FLAGS_2(cond, TCG_CALL_NO_RWG_SE, i32, i32, i32) +DEF_HELPER_FLAGS_4(cinc, TCG_CALL_NO_RWG_SE, i64, i32, i32, i64, i64) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 2f2d8bd..cd2dfe6 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1497,6 +1497,16 @@ out: tcg_temp_free_i64(tcg_addr); } +static void handle_cinc(DisasContext *s, uint32_t insn) +{ + int rd = get_reg(insn); + int rn = get_bits(insn, 5, 5); + int rm = get_bits(insn, 16, 5); + TCGv_i32 tcg_insn = tcg_const_i32(insn); + + gen_helper_cinc(cpu_reg(rd), pstate, tcg_insn, cpu_reg(rn), cpu_reg(rm)); +} + /* SIMD ORR */ static void handle_simdorr(DisasContext *s, uint32_t insn) { @@ -2056,6 +2066,13 @@ void disas_a64_insn(CPUARMState *env, DisasContext *s) handle_ld_literal(s, insn); } break; + case 0x1a: + if ((insn & 0x3fe00800) == 0x1a800000) { + handle_cinc(s, insn); + } else { + unallocated_encoding(s); + } + break; default: unallocated_encoding(s); break; -- 1.7.12.4
