On Fri, Aug 30, 2013 at 4:17 AM, Antony Pavlov <[email protected]> wrote: > On Thu, 29 Aug 2013 11:44:38 +0100 > Peter Maydell <[email protected]> wrote: > >> On 29 August 2013 10:33, Antony Pavlov <[email protected]> wrote: >> > This is slightly altered version of ARM946E-S CPU code >> > from EOS QEMU (Magic Lantern project) so nearly all >> > credits go to @a1ex. >> > >> > ARM946E-S Technical Reference Manual can be found here: >> > http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0201d/index.html >> >> I think the CPU we label "arm946" *is* an ARM946E-S -- there's >> no other TRM or variant of the 946 listed on the ARM website. >> If we're inaccurate about something we should just fix it (and >> that should be safe since there's no existing board model which >> uses the 946). > > I have just run barebox on conventional "arm946" qemu CPU. It works fine. > IMHO just now we can drop this patch. > > If Magic Lantern or CHDK need some specific initial CPU CP15 register state > then we can fix it in the platform code without defining new CPU type. > > Any comments?
Object properties the solution? Regards, Peter > > -- > Best regards, > Antony Pavlov >
