On Thu, Aug 08, 2013 at 12:21:32PM +0200, Gerd Hoffmann wrote: > On 08/08/13 11:52, Michael S. Tsirkin wrote: > > On Thu, Aug 08, 2013 at 10:57:44AM +0200, Gerd Hoffmann wrote: > >> On 08/08/13 10:37, Michael S. Tsirkin wrote: > >>> On Thu, Aug 08, 2013 at 09:57:39AM +0200, Gerd Hoffmann wrote: > >>>> Also coreboot and seabios use different values for pmbase. coreboot on > >>>> q35 maps the pmbase below 0x1000. Which surely makes sense. When we > >>>> don't place chipset stuff at 0xb000 we can assign the 0xb000->0xbfff > >>>> window to a pci bridge instead.
Re-reading this - if this has value, can't we generalize it and make all firmware behave the same, getting values from QEMU? > >>> > >>> Yes, this might be useful. But I don't think it's required to > >>> use linker to patch ACPI tables for this - we can write ASL code to read > >>> the register back from device configuration, instead. > >> > >> No, we can't, because the address is in the FADT. > >> > >> cheers, > >> Gerd > > > > I see. Yes, PM base is there, this in fact makes it possible > > to patch it by linker in a sane way. > > Exactly. Likewise the mmconf xbar config in the MCFG table. > > But to make addresses usable to devices they also need to be declared in > > the _CRS for the PCI root, correct? Which is code in DSDT. > > Yes, the address ranges used for pci devices (aka 32bit + 64bit pci > window) need to be there. Well, placing in SSDT, then referencing from > DSDT works too, and this is what seabios does today to dynamically > adjust stuff. Fixing up the SSDT using the linker is probably easier as > we generate it anyway. > > cheers, > Gerd Yes but as I said, this makes things messy, since AML encoding for numbers isn't fixed width. -- MST
