On Thu, Aug 08, 2013 at 10:51:59AM +0200, Gerd Hoffmann wrote: > On 08/08/13 10:22, Michael S. Tsirkin wrote: > > On Thu, Aug 08, 2013 at 09:57:39AM +0200, Gerd Hoffmann wrote: > >> Hi, > >> > >>>> Huh? The 32bit window is sized according to the installed memory. > >>>> That > >>>> logic is in seabios and you'll try to move it to qemu, using pci-info. > >>>> It wasn't in qemu before ... > >>> > >>> The logic is in hw/i386/pc_piix.c and always was. > >> > >> What exactly you are refering to? > > > > pc_init1 which picks addresses and passes them on to > > i440fx_init. > > Yep. qemu figured where it wants map memory. The unused 32bit address > space goes into the pci hole. cmos memory size is set accordingly. > seabios gets the memory size from cmos, then it knows where the pci hole > starts. seabios rounds it up (i.e. may leave some of it unused) to be > able to cover the complete hole with a single mtrr entry, but that isn't > a issue and can be changed if needed. The mtrr thing is more or less > cosmetical anyway in a virtual machine. > > >> Memory configuration is in the cmos, firmware can figure where it can > >> place pci devices from that. There is no need for a new interface. > > > > The assumption being that whatever is not memory is PCI? > > I'm not sure that's right. > > Maybe not in general, but I'm pretty sure for the x86 chipsets we are > emulating it is.
I think this is the basic question. Speaking about PIIX: http://download.intel.com/design/chipsets/datashts/29054901.pdf it only supported 1G RAM and 32 bit PCI. What happened with RAM below 1G is this: top of RAM to 0xfec00000 is PCI - this is emulated correctly fec10000 to ffe00000 is PCI - this is not emulated correctly What happens with RAM >1G is all PV, it doesn't exist on real hardware. Re-adding qemu-devel. Can you please keep it Cc'd? -- MST
